Model Abstraction for Formal Veri cation

As the complexity of circuit designs grows, designers look toward formal veri cation to achieve better test coverage for validating complex designs. However, this approach is inherently computationally intensive, and hence, only small designs can be veri ed using this method. To achieve better performance, model abstraction is necessary. Model abstraction reduces the number of states necessary to perform formal veri cation while maintaining the functionality of the original model with respect to the speci cations to be veri ed. As a result, model abstraction enables large designs to be formally veri ed. In this paper, we describe three methods for model abstraction based on semantics extraction from user models to improve the performance of formal veri cation tools.